With the rapid development of computer technology, especially the increasing spread-out of portable calculating applications, more attention is paid on designing of low power, large scale integrated circuits (VLSI).
A bus-invert encoding technique for reducing data bus power consuming is disclosed in Mircea R. Stan and Wayne R Burleson, “Bus-invert Coding for Low-Power I/O”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 3, NO. I, March, 1995.
FIG. 1 schematically shows the architecture of a data bus system having the data bus encoder and decoder based on this bus-invert technique. As shown in FIG. 1, a processor 10 accesses a memory 40 via a data bus 20 and a memory controller 30. In the processor 10, when the processor 10 writes data to the memory 40, a bus-invert encoder 12 generates bus-invert encoded data and corresponding bus-invert indication bits (INV_IND) according to the data in a data buffer 11, and transmits the bus-invert encoded data and the bus-invert indication bits to a bus-invert decoder 31 in the memory controller 30 via the data bus 20. The bus-invert decoder 31 performs decoding on the received bus-invert encoded data according to the bus-invert indication bits, and writes the decoded data in the memory 40. Because this technique works better for buses having fewer bits, a further improvement is proposed to divide a bus having more bits into bit-groups having fewer bits to perform bus-invert encoding on the bit-group respectively. However, this solution has to provide a bus-invert indication bit for each of the bit-groups, and thus the bus-invert indication bits form invert-indication information. Additional lines are required to transmit the invert-indication information.
In view of the above insufficiency of the prior art, the inventors propose improvements on the data bus based on bus-invert encoding.